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outputmodeselectionforlvcmosandlvpecloutputs:y0a,y0b,y1a
…
y4b(word1)
(1)
referencedelaym(pri_reforsec_ref)andfeedbackdelayn(vcxo)phaseadjustment(word0)
(1)
pfdpulsewidthdelay(word2)
锁-detectwindow(word3)
CDCM7005
SCAS793A–JUNE2005–REVISEDJUNE2005
OUTSELxOUTxB1OUTxB0LVCMOSOUTxA1OUTxA0LVCMOSDefault
[YxB][YxA]
LVCMOS
000Active00Active
0013-state013-状态
010Inverting10Inverting
011Low11Low
OUTSELxOUTxB1OUTxB0OUTxA1OUTxA0LVCMOSDefault
[YxA]
LVPECL
1xxx0ActiveYx
1xxx13-状态
(1)ifthedifferentiallvpecloutpute.g.y0a:y0bisselected(bit2ofword1),thenonlybit7ofword1definestheoutputmodefor
y0a:y0b.thesettingsofbit8,bit9,andbit10ofword1arethereforenotrelevanttothey0a:y0b.thisappliesfortheotherlvpecl
outputsaswell.
dlym2/dlyn2dlym1/dlyn1dlym0/dlyn0phaseoffsetdefault
0000psYes
001
±
160ps
010
±
320ps
011
±
480ps
100
±
830ps
101
±
1130ps
110
±
1450ps
111
±
1750ps
(1)ifprogr.delaymisset,allyxoutputsarelaggingtothereferenceclockaccordingtothevalueset.ifprogr.ifdelaynisset;allyx
outputsareleadingtothereferenceclockaccordingtothevalueset.abovearetypicalvaluesatv
CC
=3.3v,温度=25
°
c,
pecl-outputrelatetodiv4mode.
PFD1
(1)
PFD0
(1)
PFDPulseWidth
(1)(2)
Default
(1)
001.5nsyes
013ns
104.5ns
116ns
(1)这
PFDpulsewidthdelay
getsaroundthedeadzoneofthepfdtransferfunctionandreducesphasenoiseandreferencespurs.
(2)typicalvaluesatv=3.3v
CC
,温度=25
°
c.
lockw1lockw0phase-offsetatpfdinput
(1)
Default
003.5nsyes
018.5ns
1018.5ns
11Cycleslip
(2)
(1)typicalvaluesatv
CC
=3.3v,温度=25
°
c.
(2)cycleslipoccurswhenthephaseshiftatthepfdisgreaterthanoneperiodofthefrequency.itisacomplete(integernumber)循环
jump,i.e.,causebyaloss-的-lockofthepll.
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