www.德州仪器.com
s0080-01
电源_向下
锁_输出
锁_在
80k
5pF
pll_锁
输出
CDCM7005
锁
t
数字的 锁 发现
V = 0.55 v
高 CC
V = 0.35 v
低 CC
输出-的-锁
V
输出
s0081-01
电源_向下
锁_输出
锁_在
100 一个
(锁)
100 一个
(输出-的-锁)
80k
5pF
C
pll_锁
输出
锁
t
V = 0.55 v
高 CC
V
CC
V = 0.35 v
低 CC
输出-的-锁
V
输出
V = 1/c I t
输出
例子:
为 i = 110 一个, c = 10nf, v = 3.3 v,
和 v = v = 0.55 vcc = 1.8v
t = 164 s
CC
高 输出
CDCM7005
differentiallvpecloutputsandsingle-endedlvcmosoutputs
CDCM7005
SCAS793A–JUNE2005–REVISEDJUNE2005
whenselectingthedigitalplllockoption,pll_lockwillpossiblyjitterseveraltimesbetweenlockandoutof
lockuntilastablelockisdetected.asinglelow-至-highstepcanbereachedwithawidelockdetectwindowand
highnumberofsuccessiveclockcycles.pll_lockreturnstooutoflockifjustonecycleisoutsidethelock
detectwindoworacycleslipoccurs.
figure18.digitallock-发现
whenselectingtheanalogplllockoption,thehigh-pulsesloadtheexternalcapacitorviatheinternal110-µa
currentsourceuntillogichigh-levelisreached.因此,moretimeisneededtodetectlogichighlevel,但是
jitteringofpll_lockwillbesuppressedincaseofdigitallock.thetimepll_lockneedstoreturntooutof
lockdependsonthelevelofV
输出
,whenthecurrentsourcestartstounloadtheexternalcapacitor.
figure19.analoglock-发现
TheCDCM7005supportsupto5
×
LVPECLoutputsor10
×
lvcmos/lvttloutputsoranycombinationof
这些.thesingle-endedlvcmosoutputsarearrangedinpairswhichmeanbothoutputsofalvcmospair
havethesamefrequencybutcanseparatelybedisabledorinverted.thepowerupoutputarrangementisfive
lvpecl(defaultsetting).
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