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DIGITALINPUTSANDTIMING
DigitalInputs
da[11:0]
db[11:0]
睡眠
clka/b
wrta/b
内部的
数字的 在
DVDD
DGND
GSET
模式
内部的
数字的 在
DVDD
DGND
InputInterfaces
DAC5662
SLAS425–JULY2004
ThedatainputportsoftheDAC5662acceptastandardpositivecodingwithdatabitD11beingthemost
significantbit(msb).theconverteroutputssupportaclockrateofupto200msps.thebestperformancewill
typicallybeachievedwithasymmetricdutycycleforwriteandclock;不管怎样,thedutycyclemayvaryaslong
asthetimingspecificationsaremet.similarly,thesetupandholdtimesmaybechosenwithintheirspecified
限制.
alldigitalinputsofthedac5662arecmoscompatible.figure16andfigure17showschematicsofthe
equivalentcmosdigitalinputsofthedac5662.the12-bitdigitaldatainputfollowstheoffsetpositivebinary
codingscheme.thedac5662isdesignedtooperatewithadigitalsupply(dvdd)of3vto3.6v.
figure16.cmos/ttldigitalequivalentinputwithinternalpulldownresistor
figure17.cmos/ttldigitalequivalentinputwithinternalpullupresistor
thedac5662featurestwooperatingmodesselectedbythemodepin,asshowninthefollowingtable
•
fordual-businputmode,thedeviceessentiallyconsistsoftwoseparatedacs.eachdachasitsown
separatedatainputbus,clockinput,anddatawritesignal(datalatch-在).
•
insingle-businterleavedmode,thedatashouldbepresentedinterleavedatthei-channelinputbus.这
q-channelinputbusisnotusedinthismode.theclockandwriteinputarenowsharedbybothdacs.
MODEPIN
ModepinconnectedtoDGNDModepinconnectedtoDVDD
businputsingle-businterleavedmode,clockandwriteinputequalforbothdual-busmode,dacsoperate
DACsindependently
12
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