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双-busdatainterfaceandtiming
Valid 数据
d[11:0]
t
su
t
h
t
lat
t
pd
t
settle
wrt1/
WRT2
clk1/
CLK2
IOUT
或者
IOUT
t
1ph
单独的-businterleaveddatainterfaceandtiming
DAC5662
SLAS425–JULY2004
indual-busmode,themodepinisconnectedtodvdd.thetwoconverterchannelswithinthedac5662consist
oftwoindependent,12-位,paralleldataports.eachdacchanneliscontrolledbyitsownsetofwrite(wrta,
wrtb)andclock(clka,clkb)线条.thewrtlinescontrolthechannelinputlatchesandtheclklines
controlthedaclatches.thedataisfirstloadedintotheinputlatchbyarisingedgeofthewrtline
theinternaldatatransferrequiresacorrectsequenceofwriteandclockinputs,sinceessentiallytwoclock
domainshavingequalperiods(butpossiblydifferentphases)areinputtothedac5662.thisisdefinedbya
minimumrequirementofthetimebetweentherisingedgeoftheclockandtherisingedgeofthewriteinputs.
ThisessentiallyimpliesthattherisingedgeofCLKmustoccuratthesametimeorbeforetherisingedgeofthe
wrtsignal.aminimumdelayof2nsshouldbemaintainediftherisingedgeoftheclockoccursaftertherising
edgeofthewrite.notethattheseconditionsaresatisfiedwhentheclockandwriteinputsareconnected
externally.notethatallspecificationsweremeasuredwiththewrtandclklinesconnectedtogether.
figure18.dualbusmodeoperation
insingle-businterleavedmode,themodepinisconnectedtodgnd.figure19showsthetimingdiagram.在
interleavedmode,thei-andq-channelssharethewriteinput(wrtiq)andupdateclock(clkiqandinternal
clkdaciq).multiplexinglogicdirectstheinputwordatthei-channelinputbustoeitherthei-channelinputlatch
(selectiqishigh)ortotheq-channelinputlatch(selectiqislow).whenselectiqishigh,thedatavalue
intheq-channellatchisretainedbypresentingthelatchoutputdatatoitsinputagain.whenselectiqislow,
thedatavalueinthei-channellatchisretainedbypresentingthelatchoutputdatatoitsinput.
ininterleavedmode,thei-channelinputdatarateistwicetheupdaterateofthedaccore.asindual-busmode,
itisimportanttomaintainacorrectsequenceofwriteandclockinputs.theedge-triggeredflip-flopslatchthei-
andq-channelinputwordsontherisingedgeofthewriteinput(wrtiq).thisdataispresentedtothei-和
q-daclatchesonthefollowingfallingedgeofthewriteinputs.thedac5662clockinputisdividedbyafactorof
twobeforeitispresentedtothedaclatches.
correctpairingofthei-andq-channeldataisdonebyresetiq.ininterleavedmode,theclockinputclkiqis
dividedbytwo,whichwouldtranslatetoanon-deterministicrelationbetweentherisingedgesoftheclkiqand
clkdaciq.resetiqensures,不管怎样,thatthecorrectpositionoftherisingedgeofclkdaciqwithrespect
tothedataattheinputofthedaclatchisdetermined.clkdaciqisdisabled(低)whenresetiqishigh.
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