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描述/orderinginformation(持续)
TG
C
C
TG
C
C
TG
C
C
C
TG
C
C
前
CLK
D
CLR
Q
Q
C
7
2
6
5
3
1
SN74LVC2G74
singlepositive-边缘-triggeredd-typeflip-flop
WITHCLEARANDPRESET
SCES203K–APRIL1999–REVISEDJUNE2005
alowlevelatthepreset(前)orclear(clr)inputsetsorresetstheoutputs,regardlessofthelevelsofthe
otherinputs.whenpreandclrareinactive(高),dataatthedata(d)inputmeetingthesetuptime
requirementsistransferredtotheoutputsonthepositive-goingedgeoftheclockpulse.clocktriggeringoccurs
atavoltagelevelandisnotrelateddirectlytotherisetimeoftheclockpulse.followingthehold-timeinterval,
dataatthedinputcanbechangedwithoutaffectingthelevelsattheoutputs.
thisdeviceisfullyspecifiedforpartial-电源-downapplicationsusingi
止
.thei
止
circuitrydisablestheoutputs,
preventingdamagingcurrentbackflowthroughthedevicewhenitispowereddown.
FUNCTIONTABLE
INPUTSOUTPUTS
PRECLRCLKDQQ
LHXXHL
HLXXLH
LLXXH
(1)
H
(1)
HH
↑
HHL
HH
↑
LLH
HHLXQ
0
Q
0
(1)thisconfigurationisnonstable;thatis,itdoesnotpersistwhenpreorclrreturnstoitsinactive
(高)水平的.
logicdiagram(positivelogic)
2
: 点此下载
