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资料编号:546022
 
资料名称:ADS8412IPFBT
 
文件大小: 736.78K
   
说明
 
介绍:
16-BIT, 2 MSPS, UNIPOLAR DIFFERENTIAL INPUT, MICROPOWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE
 
 


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本平台电子爱好着纯手工中文简译:截至2020/5/17日,支持英文词汇500个
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TIMINGCHARACTERISTICS
ADS8412
SLAS384A–JUNE2003–REVISEDDECEMBER2004
Allspecificationstypicalat–40
°
Cto85
°
c,+va=+vbd=5v
(1)(2)(3)
PARAMETERMINTYPMAXUNIT
t
CONV
Conversiontime340400ns
t
ACQ
Acquisitiontime100ns
t
pd1
CONVSTlowtoBUSYhigh30ns
t
pd2
propagationdelaytime,endofconversiontobusylow5ns
t
w1
pulseduration,convstlow20ns
t
su1
setuptime,cslowtoconvstlow0ns
t
w2
pulseduration,convsthigh20ns
CONVSTfallingedgejitter10ps
t
w3
pulseduration,busysignallowmin(t
ACQ
)ns
t
w4
pulseduration,busysignalhigh370ns
holdtime,firstdatabusdatatransition(rdlow,orcslowforread
t
h1
40ns
循环,orbyteinputchanges)afterconvstlow
t
d1
delaytime,cslowtordlow(orbusylowtordlow)0ns
t
su2
setuptime,rdhightocshigh0ns
t
w5
pulseduration,rdlow50ns
t
en
enabletime,rdlow(orcslowforreadcycle)todatavalid20ns
t
d2
delaytime,dataholdfromrdhigh0ns
t
d3
delaytime,byterisingedgeorfallingedgetodatavalid220ns
t
w6
pulseduration,rdhigh20ns
t
w7
pulseduration,cshigh20ns
holdtime,lastrd(orcsforreadcycle)risingedgetoconvst
t
h2
50ns
fallingedge
t
su3
setuptime,bytetransitiontordfallingedge0ns
t
h3
holdtime,bytetransitiontordfallingedge0ns
t
dis
disabletime,rdhigh(cshighforreadcycle)to3-stateddatabus20ns
t
d5
delaytime,endofconversiontomsbdatavalid10ns
bytetransitionsetuptime,frombytetransitiontothenextbyte
t
su4
50ns
转变
t
d6
delaytime,csrisingedgetobusyfallingedge50ns
t
d7
delaytime,busyfallingedgetocsrisingedge50ns
setuptime,fromthefallingedgeofconvst(usedtostartthevalid
转换)tothenextfallingedgeofconvst(whencs=0and
t
su(ab)
60340ns
convstusedtoabort)ortothenextfallingedgeofcs(whencsis
usedtoabort)
setuptime,fallingedgeofconvsttoreadvaliddata(msb)从
t
su5
最大值(t
CONV
)+max(t
d5
)ns
currentconversion
holdtime,数据(msb)frompreviousconversionholdvalidfromfalling
t
h4
最小值(t
CONV
)ns
edgeofCONVST
(1)allinputsignalsarespecifiedwitht
r
=t
f
=5ns(10%to90%of+vbd)andtimedfromavoltagelevelof(v
IL
+V
IH
)/2.
(2)seetimingdiagrams.
(3)alltimingsaremeasuredwith20pfequivalentloadsonalldatabitsandbusypins.
5
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