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布局
ADS8406
SLAS426A–AUGUST2004–REVISEDDECEMBER2004
resetisanasynchronousactivelowinputsignal(thatworksindependentlyofcs).minimumresetlowtime
is25ns.currentconversionwillbeabortednolaterthan50nsaftertheconverterisintheresetmode.在
增加,alloutputlatchesarecleared(settozero's)afterreset.theconvertergoesbacktonormaloperation
modenolaterthan20nsafterresetinputisbroughthigh.
theconverterstartsthefirstsamplingperiod20nsaftertherisingedgeofreset.anysamplingperiodexcept
fortheoneimmediatelyafteraRESETisstartedwiththefallingedgeofthepreviousBUSYsignalorthefalling
edgeofcs,whicheverislater.
anotherwaytoresetthedeviceisthroughtheuseofthecombinationofcsandconvst.thisisusefulwhen
thededicatedRESETpinistiedtothesystemresetbutthereisaneedtoabortonlytheconversioninaspecific
转换器.sincethebusysignalisheldhighduringtheconversion,eitheroneoftheseconditionstriggersan
internalself-clearresettotheconverterjustthesameasaresetviathededicatedresetpin.theresetdoes
nothavetobeclearedasforthededicatedresetpin.aresetcanbestartedwitheitherofthetwofollowing
步伐.
•
issueaconvstwhencsislowandaconversionisinprogress.thefallingedgeofconvstmustsatisfy
thetimingasspecifiedbythetimingparametert
su(ab)
mentionedinthetimingcharacteristicstabletoensure
areset.thefallingedgeofconvststartsareset.timingisthesameasaresetusingthededicated
resetpinexcepttheinstanceofthefallingedgeisreplacedbythefallingedgeofconvst.
•
issueacswhileaconversionisinprogress.thefallingedgeofcsmustsatisfythetimingasspecifiedby
thetimingparametert
su(ab)
mentionedinthetimingcharacteristicstabletoensureareset.thefallingedgeof
cscausesareset.timingisthesameasaresetusingthededicatedresetpinexcepttheinstanceofthe
fallingedgeisreplacedbythefallingedgeofcs.
resetisnotrequiredafterpoweron.aninternalpower-在-resetcircuitgeneratesthereset.toensurethatall
oftheregistersarecleared,thethreeconversioncyclesmustbegiventotheconverterafterpoweron.
foroptimumperformance,careshouldbetakenwiththephysicallayoutoftheads8406circuitry.
astheads8406offerssingle-supplyoperation,itisoftenusedincloseproximitywithdigitallogic,
微控制器,微处理器,anddigitalsignalprocessors.themoredigitallogicpresentinthedesignand
thehighertheswitchingspeed,themoredifficultitistoachievegoodperformancefromtheconverter.
thebasicsararchitectureissensitivetoglitchesorsuddenchangesonthepowersupply,涉及,地面
connectionsanddigitalinputsthatoccurjustpriortolatchingtheoutputoftheanalogcomparator.因此,驱动
anysingleconversionforann-bitsarconverter,thereareatleastn
windows
inwhichlargeexternaltransient
voltagescanaffecttheconversionresult.suchglitchesmightoriginatefromswitchingpowersupplies,nearby
digitallogic,orhighpowerdevices.
thedegreeoferrorinthedigitaloutputdependsonthereferencevoltage,布局,andtheexacttimingofthe
externalevent.
onaverage,theads8406drawsverylittlecurrentfromanexternalreference,asthereferencevoltageis
internallybuffered.ifthereferencevoltageisexternalandoriginatesfromanopamp,makesurethatitcandrive
thebypasscapacitororcapacitorswithoutoscillation.a0.1-µfbypasscapacitoranda1-µfstoragecapacitor
arerecommendedfrompin1(refin)directlytopin48(refm).refmandagndshouldbeshortedonthe
samegroundplaneunderthedevice.
theagndandbdgndpinsshouldbeconnectedtoacleangroundpoint.inallcases,thisshouldbethe
analogground.avoidconnectionswhichareclosetothegroundingpointofamicrocontrollerordigitalsignal
处理器.ifrequired,runagroundtracedirectlyfromtheconvertertothepowersupplyentrypoint.theideal
layoutconsistsofananaloggroundplanededicatedtotheconverterandassociatedanalogcircuitry.
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