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外部 时钟 信号
(toggling 0 −V
DDIO
)
XCLKIN
X2
NC
X1
外部 时钟 信号
(toggling 0 −V
DD
)
XCLKIN
X2
NC
X1
C
L1
X2X1
结晶
C
L2
XCLKIN
tms320f2808,tms320f2806
tms320f2801,ucd9501
DigitalSignalProcessors
SPRS230F–OCTOBER2003–REVISEDSEPTEMBER2005
2.a1.8-vexternaloscillatorcanbedirectlyconnectedtothex1pin.thex2pinshouldbeleft
unconnectedandthexclkinpintiedlow.thelogic-highlevelinthiscaseshouldnotexceedv
DD
.
thethreepossibleinput-clockconfigurationsareshowninfigure3-9通过figure3-11
figure3-9.usinga3.3-vexternaloscillator
figure3-10.usinga1.8-vexternaloscillator
figure3-11.usingtheinternaloscillator
3.6.1.1externalreferenceoscillatorclockoption
thetypicalspecificationsfortheexternalquartzcrystalforafrequencyof20mhzarelistedbelow:
•
fundamentalmode,parallelresonant
•
C
L
(loadcapacitance)=12pf
•
C
L1
=C
L2
=24pF
•
C
调往
=6pF
•
ESRrange=30to60
Ω
tirecommendsthatcustomershavetheresonator/crystalvendorcharacterizetheoperationoftheir
devicewiththedspchip.theresonator/crystalvendorhastheequipmentandexpertisetotunethetank
电路.thevendorcanalsoadvisethecustomerregardingthepropertankcomponentvaluesthatwill
produceproperstartupandstabilityovertheentireoperatingrange.
3.6.1.2pll-basedclockmodule
the280xdeviceshaveanon-碎片,pll-basedclockmodule.thismoduleprovidesallthenecessary
clockingsignalsforthedevice,aswellascontrolforlow-powermodeentry.thepllhasa4-bitratio
controlpllcr[div]toselectdifferentcpuclockrates.thewatchdogmoduleshouldbedisabledbefore
writingtothepllcrregister.itcanbere-使能(ifneedbe)afterthepllmodulehasstabilized,这个
takes131072oscclkcycles.
FunctionalOverview
42
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