www.德州仪器.com
TIMINGREQUIREMENTS
(1)(2)
1
2
3
5
4
6
10
16
14
12
1
9
SCLK
SDO
Hi−Z
自动 电源
−
向下
7
8
last sclk= 16 为ADS 7866
14为ADS 7867
12为ADS 7868
Hi−Z
自动 电源
−
向下
2
t
su(csf−fsclkf)
t
c(sclk)
t
wh(sclk)
t
wl(sclk)
t
wh(cs)
t
su(lsbz−csf)
t
dis(eoc−sdoz)
t
su(csf−fsclkf)
t
d(csf−sdovalid)
“0” “0” “0”
t
转变
“0” “0” “0”
t
h(sclkf−sdovalid)
t
d(sclkf−sdovalid)
t
d(csf−sdovalid)
t
样本
“0”
支撑 EOC
CS
t
循环
MSB MSB−1 MSB−2 MSB−3 MSB−4 MSB−5
LSB
ADS7866
ADS7867
ADS7868
SLAS465–JUNE2005
at–40°cto85°c,f
SCLK
=3.4mhzif1.6v
≤
V
DD
≤
3.6v;f
SCLK
=1.7mhzif1.2v
≤
V
DD
<1.6v,50-pfloadonsdopin,
unlessotherwisenoted
PARAMETERTESTCONDITIONSMINTYPMAXUNIT
t
样本
Sampletimet
su(csf-fsclkf)
+2
×
t
c(sclk)
µs
ADS786613
×
t
c(sclk)
t
转变
ConversiontimeADS786711
×
t
c(sclk)
µs
ADS78689
×
t
c(sclk)
1.2v
≤
V
DD
<1.6vsee
(3)
100
1.6v
≤
V
DD
<1.8vsee
(3)
100
t
c(sclk)
Cycletimeµs
1.8v
≤
V
DD
<2.5vsee
(3)
50
2.5v
≤
V
DD
≤
3.6vsee
(3)
6.7
t
wh(sclk)
pulseduration0.4
×
t
c(sclk)
0.6
×
t
c(sclk)
ns
t
wl(sclk)
pulseduration0.4
×
t
c(sclk)
0.6
×
t
c(sclk)
ns
1.2v
≤
V
DD
<1.6v192
t
su(csf-fsclkf)
setuptime1.6v
≤
V
DD
<1.8v55ns
1.8v
≤
V
DD
≤
3.6v55
1.2v
≤
V
DD
<1.6v65
t
d(csf-sdovalid)
delaytime1.6v
≤
V
DD
<1.8v55ns
1.8v
≤
V
DD
≤
3.6v55
1.2v
≤
V
DD
<1.6v20
t
h(sclkf-sdovalid)
holdtime1.6v
≤
V
DD
<1.8v10ns
1.8v
≤
V
DD
≤
3.6v10
1.2v
≤
V
DD
<1.6v140
t
d(sclkf-sdovalid)
delaytime1.6v
≤
V
DD
<1.8v140ns
1.8v
≤
V
DD
≤
3.6v140
1.2v
≤
V
DD
<1.6v1080
t
dis(eoc-sdoz)
disabletime1.6v
≤
V
DD
<1.8v760ns
1.8v
≤
V
DD
≤
3.6v760
1.2v
≤
V
DD
<1.6v20
t
wh(cs)
pulseduration1.6v
≤
V
DD
<1.8v10ns
1.8v
≤
V
DD
≤
3.6v10
1.2v
≤
V
DD
<1.6v20
t
su(lsbz-csf)
setuptime1.6v
≤
V
DD
<1.8v10ns
1.8v
≤
V
DD
≤
3.6v10
(1)allinputsignalsarespecifiedwitht
r
=t
f
=5ns(10%to90%ofv
DD
)andtimedfromavoltagelevelof(v
IL
+V
IH
)/2.
(2)seetimingdiagraminFigure1.
(3)mint
c(sclk)
isdeterminedbytheMint
样本
ofthespecificresolutionandsupplyvoltage.看
acquisitiontime,conversiontime,和
TotalCycleTime
sectionforfurtherdetails.
figure1.timingdiagram
9
: 点此下载
