#define	BaseAddr	0x6000000
#define	RWPORT	(BaseAddr+0x10)	/* dma read write address, form 0x10 - 0x17 */
#define	RstAddr (BaseAddr+0x18)	/* reset register, 0x18, 0x1a, 0x1c, 0x1e even address is recommanded */

/* page 0 */
#define	Pstart	(BaseAddr+1)	/* page start */
#define	Pstop	(BaseAddr+2)	/* page stop */
#define	BNRY	(BaseAddr+3)	
#define	TPSR	(BaseAddr+4)	/* transmit page start */
#define	TBCR0	(BaseAddr+5)
#define	TBCR1	(BaseAddr+6)
#define	ISR		(BaseAddr+7)	/* interrupt status register */

#define	RSAR0	(BaseAddr+8)	/* dma read address */
#define	RSAR1	(BaseAddr+9)
#define	RBCR0	(BaseAddr+10)	/* dma read byte count */
#define	RBCR1	(BaseAddr+11)

#define	RCR		(BaseAddr+12)	/* receive config */
#define	TCR		(BaseAddr+13)	/* transmit config */
#define	DCR		(BaseAddr+14)	/* data config */
#define	IMR		(BaseAddr+15)	/* interrupt mask */

#define	ID8019L	(BaseAddr+10)
#define	ID8019H	(BaseAddr+11)

/* page 1 */
#define	PAR0	(BaseAddr+1)
#define	PAR1	(BaseAddr+2)
#define	PAR2	(BaseAddr+3)
#define	PAR3	(BaseAddr+4)
#define	PAR4	(BaseAddr+5)
#define	PAR6	(BaseAddr+6)

#define	CURR	(BaseAddr+7)		
#define	MAR0	(BaseAddr+8)
#define	MAR1	(BaseAddr+9)
#define	MAR2	(BaseAddr+10)
#define	MAR3	(BaseAddr+11)
#define	MAR4	(BaseAddr+12)
#define	MAR5	(BaseAddr+13)
#define	MAR6	(BaseAddr+14)
#define	MAR7	(BaseAddr+15)

/* page 2 */

/* page 3 */
#define	CR9346	(BaseAddr+1)
#define	CONFIG0	(BaseAddr+3)
#define	CONFIG1	(BaseAddr+4)
#define	CONFIG2	(BaseAddr+5)
#define	CONFIG3	(BaseAddr+6)